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The signal DEBUGEN# (CONF0) from the base board to the module is necessary to
allow switching a connection on and off between the system reset and the JTAG
reset.
Signal
DEBUGEN#
DEBUGEN#
State
High
Low
Description
Switch is on, TRST# and PWRGOOD are connected (default)
Switch is off, TRST# and PWRGOOD are disconnected
..................................................................................
At the module a pull up resistor is provided on the DEBUGEN# signal. Therefore only
a jumper to GND is necessary on the base board.
Chip selects
Chip select
memory map
Name
CPU Signal
Pin
Address
Size [Mb]
Usage
Comments
name
Range
SCS0#
SCS0#
H15
0x3000_0000-
128
SDRAM bank 0
First bank on
0x37FF_FFFF
module
SCS1#
SCS1#
D17
0x3800_0000-
128
SDRAM bank 1
0x3FFF_FFFF
RCS0#
RCS0#
A2
0x0000_0000-
64
not available
0x03FF_FFFF
RCS1#
RCS1#
A1
0x0800_0000-
64
external, RCS1#
0x083F_FFFF
RCS2#
RCS2#
B3
0x1000_0000-
64
external, RCS2#
0x103F_FFFF
RCS3#
RCS3#
C1
0x1800_0000-
64
external, RCS3#
0x183F_FFFF
RCS4#
RCS4#
C4
0x2000_0000-
64
external, RCS4#
0x203F_FFFF
RCS5#
RCS5#
E4
0x2800_0000-
64
internal, RCS5#
Used for Ethernet
www.digiembedded.com
0x283F_FFFF
Controller
24
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